HCS08 datasheet(76/374 Pages) NXP

76 / 374 page

Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

5.7.5

System Options Register 2 (SOPT2)

5.7.6

System Device Identification Register (SDIDH, SDIDL)

This read-only register is included so host development systems can identify the HCS08 derivative and

revision number. This allows the development software to recognize where specific memory blocks,

registers, and control bits are located in a target MCU.

321

COPCLKS1

COPW1

SPI1FE

SPI2FE

ACIC

Reset

000

110

= Unimplemented or Reserved

1 This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-6. System Options Register 2 (SOPT2)

Table 5-7. SOPT2 Register Field Descriptions

Field

Description

COPCLKS

COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.

0 Internal 1 kHz LPO clock is source to COP.

1 Bus clock is source to COP.

COPW

COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence

to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the

first 75% of the selected period will reset the MCU.

0 Normal COP operation.

1 Window COP operation.

SPI1FE

SPI1 Ports Input Filter Enable

0 Disable input filter on SPI1 port pins to allow for higher maximum SPI baud rate.

1 Enable input filter on SPI1 port pins to eliminate noise and restrict maximum SPI baud rate.

SPI2FE

SPI2 Ports Input Filter Enable

0 Disable input filter on SPI2 port pins to allow for higher maximum SPI baud rate.

1 Enable input filter on SPI2 port pins to eliminate noise and restrict maximum SPI baud rate.

ACIC

Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM input channel 0.

0 ACMP output not connected to TPM input channel 0.

1 ACMP output connected to TPM input channel 0.

321

ID11

ID10

ID9

ID8

Reset

——

000

= Unimplemented or Reserved

Figure 5-7. System Device Identification Register — High (SDIDH)

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