HCS08 datasheet(97/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

321

PTGPE5

PTGPE4

PTGPE3

PTGPE2

PTGPE1

PTGPE0

Reset

000

Figure 6-34. Internal Pullup Enable for Port G Bits (PTGPE)

Table 6-33. PTGPE Register Field Descriptions

Field

Description

5:0

PTGPEn

Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is

enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and

the internal pullup devices are disabled.

0 Internal pullup device disabled for port G bit n.

1 Internal pullup device enabled for port G bit n.

321

PTGSE5

PTGSE4

PTGSE3

PTGSE2

PTGSE1

PTGSE0

Reset

011

111

Figure 6-35. Output Slew Rate Control Enable for Port G Bits (PTGSE)

Table 6-34. PTGSE Register Field Descriptions

Field

Description

5:0

PTGSEn

Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew

rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have

no effect.

0 Output slew rate control disabled for port G bit n.

1 Output slew rate control enabled for port G bit n.

321

PTGDS5

PTGDS4

PTGDS3

PTGDS2

PTGDS1

PTGDS0

Reset

000

Figure 6-36. Output Drive Strength Selection for Port G (PTGDS)

Table 6-35. PTGDS Register Field Descriptions

Field

Description

5:0

PTGDSn

Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high

output drive for the associated PTG pin.

0 Low output drive enabled for port G bit n.

1 High output drive enabled for port G bit n.

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