HCS08 datasheet(69/374 Pages) NXP

69 / 374 page

Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pullup

or pull-down depending on the polarity chosen. If the user desires to use an external pullup or pull-down,

the IRQPDD can be written to a 1 to turn off the internal device.

BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act

as the IRQ input.

NOTE

This pin does not contain a clamp diode to VDD and must not be driven

above VDD. The voltage measured on the internally pulled up IRQ pin may

be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled

all the way to VDD.

5.5.2.2

Edge and Level Sensitivity

The IRQMOD control bit re-configure the detection logic so it detects edge events and pin levels. In this

edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin

changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)

as long as the IRQ pin remains at the asserted level.

5.5.3

Interrupt Vectors, Sources, and Local Masks

Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the

bottom of the table. The high-order byte of the address for the interrupt service routine is located at the

first address in the vector address column, and the low-order byte of the address for the interrupt service

routine is located at the next higher address.

When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt

enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in

the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU

registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.

Processing then continues in the interrupt service routine.

Table 5-1. Vector Summary (from Lowest to Highest Priority)

Vector

Number

Address

(High/Low)

Vector Name

Module

Source

Enable

Description

31 to 30

0xFFC0:FFC1

0xFFC2:FFC3

Unused vector space (available for user program)

0xFFC4:FFC5

Vrtc

System

control

RTIF

RTIE

RTC real-time interrupt

0xFFC6:FFC7

Viic

IIC

IICIF

IICIE

IIC

0xFFC8:FFC9

Vacmp

ACMP

ACF

ACIE

ACMP

0xFFCA:FFCB

Vadc

ADC

COCO

AIEN

ADC

0xFFCC:FFCD

Vkeyboard

KBI

KBF

KBIE

Keyboard pins

0xFFCE:FFCF

Vsci2tx

SCI2

TDRE

TIE

TCIE

SCI2 transmit

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