HCS08 datasheet(85/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

321

PTAPE5

PTAPE4

PTAPE3

PTAPE2

PTAPE1

PTAPE0

Reset

000

Figure 6-4. Internal Pullup Enable for Port A (PTAPE)

Table 6-3. PTADD Register Field Descriptions

Field

Description

[5:0]

PTAPE[5:0]

Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is

enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and

the internal pullup devices are disabled.

0 Internal pullup device disabled for port A bit n.

1 Internal pullup device enabled for port A bit n.

321

PTASE5

PTASE4

PTASE3

PTASE2

PTASE1

PTASE0

Reset

001

111

Figure 6-5. Output Slew Rate Control Enable for Port A (PTASE)

Table 6-4. PTASE Register Field Descriptions

Field

Description

5:0

PTASE[5:0]

Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew

rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have

no effect.

0 Output slew rate control disabled for port A bit n.

1 Output slew rate control enabled for port A bit n.

321

PTADS5

PTADS4

PTADS3

PTADS2

PTADS1

PTADS0

Reset

000

Figure 6-6. Output Drive Strength Selection for Port A (PTASE)

Table 6-5. PTASE Register Field Descriptions

Field

Description

5:0

PTADS[5:0]

Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high

output drive for the associated PTA pin.

0 Low output drive enabled for port A bit n.

1 High output drive enabled for port A bit n.

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