HCS08 datasheet(78/374 Pages) NXP

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Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

5.7.8

System Power Management Status and Control 2 Register

(SPMSC2)

This register is used to report the status of the low voltage warning function, and to configure the stop

mode behavior of the MCU.

Table 5-10. SPMSC1 Register Field Descriptions

Field

Description

LVWF

Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status.

0 low-voltage warning is not present.

1 low-voltage warning is present or was present.

LVWACK

Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred. To acknowledge

this low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning

is no longer present.

LVWIE

Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.

0 Hardware interrupt disabled (use polling).

1 Request a hardware interrupt when LVWF = 1.

LVDRE

Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset

(provided LVDE = 1).

0 LVD events do not generate hardware resets.

1 Force an MCU reset when an enabled low-voltage detect event occurs.

LVDSE

Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage

detect function operates when the MCU is in stop mode.

0 Low-voltage detect disabled during stop mode.

1 Low-voltage detect enabled during stop mode.

LVDE

Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation

of other bits in this register.

0 LVD logic disabled.

1 LVD logic enabled.

BGBE

Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by

ACMP or ADC module on one of its internal channels.

0 Bandgap buffer disabled.

1 Bandgap buffer enabled.

210

LVDV

LVWV

PPDF

PPDC1

PPDACK

Power-on Reset:

000

LVD Reset:

000

Any other Reset:

= Unimplemented or Reserved

u = Unaffected by reset

1 This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)

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