HCS08 datasheet(52/374 Pages) NXP

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Chapter 4 Memory

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

4.5.2

Program and Erase Times

Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be

written to set the internal clock for the flash module to a frequency (fFCLK) between 150 kHz and 200 kHz

(see Section 4.7.1, “Flash Clock Divider Register (FCDIV).”) This register can be written only once, so

normally this write is done during reset initialization. FCDIV cannot be written if the access error flag,

FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV

and erase pulses. An integer number of these timing pulses are used by the command processor to complete

a program or erase command.

Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency

of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK =1/fFCLK. The times are shown as a number

of cycles of FCLK and as an absolute time for the case where tFCLK =5 μs. Program and erase times

shown include overhead for the command state machine and enabling and disabling of program and erase

voltages.

4.5.3

Program and Erase Command Execution

The steps for executing any of the commands are listed below. The FCDIV register must be initialized and

any error flags cleared before beginning command execution. The command execution steps are:

1. Write a data value to an address in the flash array. The address and data information from this write

is latched into the flash interface. This write is a required first step in any command sequence. For

erase and blank check commands, the value of the data is not important. For page erase commands,

the address may be any address in the 512-byte page of flash to be erased. For mass erase and blank

check commands, the address can be any address in the flash memory. Whole pages of 512 bytes

are the smallest block of flash that may be erased. In the 60K version, there are two instances where

the size of a block that is accessible to the user is less than 512 bytes: the first page following RAM,

and the first page following the high page registers. These pages are overlapped by the RAM and

high page registers respectively.

NOTE

Do not program any byte in the flash more than once after a successful erase

operation. Reprogramming bits to a byte which is already programmed is

not allowed without first erasing the page in which the byte resides or mass

erasing the entire flash memory. Programming without first erasing may

disturb data stored in the flash.

Table 4-5. Program and Erase Times

Parameter

Cycles of FCLK

Time if FCLK = 200 kHz

Byte program

μs

Byte program (burst)

μs1

1 Excluding start/end overhead

Page erase

4000

20 ms

Mass erase

20,000

100 ms

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