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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HCS08 bảng dữ liệu(PDF) 39 Page - NXP Semiconductors |
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HCS08 bảng dữ liệu(HTML) 39 Page - NXP Semiconductors |
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39 / 374 page  Chapter 3 Modes of Operation MC9S08JM60 Series Data Sheet, Rev. 5 Freescale Semiconductor 39 writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2 Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Peripheral Mode Stop2 Stop3 CPU Off Standby RAM Standby Standby Flash Off Standby Parallel Port Registers Off Standby ADC Off Optionally On1 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. ACMP Off Optionally On2 2 If ACGBS in ACMPSC is set, LVD must be enabled, else in standby. MCG Off Optionally On3 3 IRCLKEN and IREFSTEN set in MCGC1, else in standby. IIC Off Standby RTC Optionally on4 4 RTCPS[3:0] in RTCSC does not equal 0 before entering stop, else off. Optionally on4 SCI Off Standby SPI Off Standby TPM Off Standby System Voltage Regulator Off Standby XOSC Off Optionally On5 5 ERCLKEN and EREFSTEN set in MCGC2, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3. I/O Pins States Held States Held USB (SIE and Transceiver) Off Optionally On6 6 USBEN in CTL is set and USBPHYEN in USBCTL0 is set, else off. USB 3.3-V Regulator Off Standby USB RAM Standby Standby |
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