HCS08 datasheet(308/374 Pages) NXP

308 / 374 page

Universal Serial Bus Device Controller (S08USBV1)

MC9S08JM60 Series Data Sheet, Rev. 5

308

Freescale Semiconductor

17.3.13 Endpoint Control Register (EPCTLn, n=0-6)

The endpoint control registers contains the endpoint control bits (EPCTLDIS, EPRXEN, EPTXEN, and

EPHSHK) for each endpoint available within the USB module for a decoded address. These four bits

define all of the control necessary for any one endpoint. The formats for these registers are shown in the

tables below. Endpoint 0 (ENDP0) is associated with control pipe 0 which is required by the USB for all

functions. Therefore, after a USBRST interrupt has been received, the microcontroller must set EPCTL0

to contain 0x0D.

321

FRM10

FRM9

FRM8

Reset

000

= Unimplemented or Reserved

Figure 17-16. Frame Number Register High (FRMNUMH)

Table 17-17. FRMNUMH Field Descriptions

Field

Description

2–0

FRM[10:8]

Frame Number — These bits represent the high order bits of the 11-bit frame number.

543

EPCTLDIS

EPRXEN

EPTXEN

EPSTALL

EPHSHK

Reset

(EP0-6)

0000

= Unimplemented or Reserved

Figure 17-17. Endpoint Control Register (EPCTLn)

Table 17-18. EPCTLn Field Descriptions

Field

Description

EPCTLDIS

Endpoint Control — This bit defines if an endpoint is enabled and the direction of the endpoint. The

endpoint enable/direction control is defined in Table 17-19.

EPRXEN

Endpoint Rx Enable — This bit defines if an endpoint is enabled for OUT transfers. The endpoint

enable/direction control is defined in Table 17-19.

EPTXEN

Endpoint Tx Enable — This bit defines if an endpoint is enabled for IN transfers. The endpoint

enable/direction control is defined in Table 17-19.

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