HCS08 datasheet(306/374 Pages) NXP

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Universal Serial Bus Device Controller (S08USBV1)

MC9S08JM60 Series Data Sheet, Rev. 5

306

Freescale Semiconductor

17.3.10 Control Register (CTL)

The CTL provides various control and configuration information for the USB module.

In/Out Transaction — This bit indicates whether the last BDT updated was for a transmit (IN) transfer or a

receive (OUT) data transfer.

0 Last transaction was a receive (OUT) data transfer

1 Last BDT updated was for transmit (IN) transfer

ODD

Odd/Even Transaction —This bit indicates whether the last buffer descriptor updated was in the odd bank of

the BDT or the even bank of the BDT, See earlier section for more information on BDT address generation.

0 Last buffer descriptor updated was in the EVEN bank

1 Last buffer descriptor updated was in the ODD bank

321

TSUSPEND

CRESUME

ODDRST

USBEN

Reset

000

Figure 17-13. Control Register (CTL)

Table 17-14. CTL Field Descriptions

Field

Description

TSUSPEND

Transaction Suspend — This bit is set by the serial interface engine (SIE) when a setup token is received,

allowing software to dequeue any pending packet transactions in the BDT before resuming token processing.

The TSUSPEND bit informs the processor that the SIE has disabled packet transmission and reception.

Clearing this bit allows the SIE to continue token processing.

0 Allows the SIE to continue token processing

1 Set by the SIE when a setup token is received; SIE has disabled packet transmission and reception.

CRESUME

Resume Signaling — Setting this bit will allow the USB module to execute resume signaling. This will allow

the USB module to perform remote wakeup. Software must set CRESUME to 1 for the amount of time

required by the USB Specification Rev. 2.0 and then clear it to 0.

0 Do not execute remote wakeup

1 Execute resume signaling - remote wakeup

ODDRST

Odd Reset — Setting this bit will reset all the buffer descriptor ODD ping-pong bits to 0 which will then specify

the EVEN descriptor bank. This bit is used with double-buffered endpoints 5 and 6. This bit has no effect on

endpoints 0 through 4.

0 Do not reset

1 Reset all the buffer descriptor ODD ping/pong bits to 0 which will then specify the EVEN descriptor bank

USBEN

USB Enable Setting this bit will enable the USB module to operate. Setting this bit causes the SIE to reset

all of its ODD bits to the BDTs. Thus, setting this bit will reset much of the logic in the SIE.

0 Disable the USB module

1 Enable the USB module for operation, will not affect Transceiver and VREG.

Table 17-13. STAT Field Descriptions (continued)

Field

Description

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