HCS08 datasheet(262/374 Pages) NXP

262 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

262

Freescale Semiconductor

In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by

the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case

the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur

in slave mode.

If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output

buffer is disabled. So SPSCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any

possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is

forced into idle state.

If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output

enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in

the bidirectional mode for the SPI system configured in slave mode.

The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed

by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or

slave again.

15.4.9

Low Power Mode Options

15.4.9.1

SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a

low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are

disabled.

15.4.9.2

SPI in Wait Mode

SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2.

•

If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode

•

If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation

state when the CPU is in wait mode.

— If SPISWAI is set and the SPI is configured for master, any transmission and reception in

progress stops at wait mode entry. The transmission and reception resumes when the SPI exits

wait mode.

– If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in

progress continues if the SPSCK continues to be driven from the master. This keeps the slave

synchronized to the master and the SPSCK.

If the master transmits data while the slave is in wait mode, the slave will continue to send out

data consistent with the operation mode at the start of wait mode (i.e., if the slave is currently

sending its SPIxDH:SPIxDL to the master, it will continue to send the same byte. Otherwise,

if the slave is currently sending the last data received byte from the master, it will continue to

send each previously receive data from the master byte).

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