HCS08 datasheet(258/374 Pages) NXP

258 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

258

Freescale Semiconductor

Figure 15-13. SPI Clock Formats (CPHA = 1)

When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not

defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto

the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the

master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the

third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,

and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the

master and slave, respectively. When CPHA = 1, the slave’s SS input is not required to go to its inactive

high level between transfers.

Figure 15-14 shows the clock formats when SPIMODE = 0 and CPHA = 0. At the top of the figure, the

eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit

8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending

on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms

applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the

MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output

pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT

waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master

SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half

BIT TIME #

(REFERENCE)

MSB FIRST

LSB FIRST

SPSCK

(CPOL = 0)

SPSCK

(CPOL = 1)

SAMPLE IN

(MISO OR MOSI)

MOSI

(MASTER OUT)

MISO

(SLAVE OUT)

SS OUT

(MASTER)

SS IN

(SLAVE)

BIT 7

BIT 0

BIT 6

BIT 1

BIT 2

BIT 5

BIT 1

BIT 6

BIT 0

BIT 7

...

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