HCS08 datasheet(257/374 Pages) NXP

257 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

257

Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE bit) in master

mode will abort a transmission in progress, force the SPI system into idle state, and reset all status bits in

the SPIxS register. To initiate a transfer after writing to SPIMODE, the SPIxS register must be read with

SPTEF = 1, and data must be written to SPIxDH:SPIxDL in 16-bit mode (SPIMODE = 1) or SPIxDL in

8-bit mode (SPIMODE = 0).

In slave mode, user software should write to SPIMODE only once to prevent corrupting a transmission in

progress.

NOTE

Data can be lost if the data length is not the same for both master and slave

devices.

15.4.5

SPI Clock Formats

To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI

system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock

formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses

between two different clock phase relationships between the clock and data.

Figure 15-13 shows the clock formats when SPIMODE = 0 (8-bit mode) and CPHA = 1. At the top of the

figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8

ending one-half SPSCK cycle after the sixteenth SPSCK edge. The MSB first and LSB first lines show the

order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown,

but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The

SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI

waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO

output from a slave. The SS OUT waveform applies to the slave select output from a master (provided

MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start

of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform

applies to the slave select input of a slave.

HCS08 bảng dữ liệu(PDF) 257 Page - NXP Semiconductors