HCS08 datasheet(253/374 Pages) NXP

253 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

253

When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately

after the previous transmission has completed.

The SPI transmit buffer empty flag (SPTEF) in the SPIxS register indicates when the transmit data buffer

is ready to accept new data. SPIxS must be read when SPTEF is set before writing to the SPI data registers,

or the write will be ignored.

Data may be read from SPIxDH:SPIxDL any time after SPRF is set and before another transfer is finished.

Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun

condition and the data from the new transfer is lost.

In 8-bit mode, only SPIxDL is available. Reads of SPIxDH will return all 0s. Writes to SPIxDH will be

ignored.

In 16-bit mode, reading either byte (SPIxDH or SPIxDL) latches the contents of both bytes into a buffer

where they remain latched until the other byte is read. Writing to either byte (SPIxDH or SPIxDL) latches

the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value

into the transmit data buffer.

15.3.6

SPI Match Registers (SPIxMH:SPIxML)

These read/write registers contain the hardware compare value, which sets the SPI match flag (SPMF)

when the value received in the SPI receive data buffer equals the value in the SPIxMH:SPIxML registers.

In 8-bit mode, only SPIxML is available. Reads of SPIxMH will return all 0s. Writes to SPIxMH will be

ignored.

In 16-bit mode, reading either byte (SPIxMH or SPIxML) latches the contents of both bytes into a buffer

where they remain latched until the other byte is read. Writing to either byte (SPIxMH or SPIxML) latches

the value into a buffer. When both bytes have been written, they are transferred as a coherent value into

the SPI match registers.

321

Bit 15

Bit 8

Reset

000

Figure 15-11. SPI Match Register High (SPIxMH)

321

Bit 7

Bit 0

Reset

000

Figure 15-12. SPI Match Register Low (SPIxML)

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