HCS08 datasheet(252/374 Pages) NXP

252 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

252

Freescale Semiconductor

15.3.5

SPI Data Registers (SPIxDH:SPIxDL)

The SPI data registers (SPIxDH:SPIxDL) are both the input and output register for SPI data. A write to

these registers writes to the transmit data buffer, allowing data to be queued and transmitted.

Table 15-8. SPIxS Register Field Descriptions

Field

Description

SPRF

SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may

be read from the SPI data register (SPIxDH:SPIxDL). SPRF is cleared by reading SPRF while it is set, then

reading the SPI data register.

0 No data available in the receive data buffer.

1 Data available in the receive data buffer.

SPMF

SPI Match Flag — SPMF is set after SPRF = 1 when the value in the receive data buffer matches the value in

SPIMH:SPIML. To clear the flag, read SPMF when it is set, then write a 1 to it.

0 Value in the receive data buffer does not match the value in SPIxMH:SPIxML registers.

1 Value in the receive data buffer matches the value in SPIxMH:SPIxML registers.

SPTEF

SPI Transmit Buffer Empty Flag — This bit is set when the transmit data buffer is empty. It is cleared by reading

SPIxS with SPTEF set, followed by writing a data value to the transmit buffer at SPIxDH:SPIxDL. SPIxS must be

read with SPTEF = 1 before writing data to SPIxDH:SPIxDL or the SPIxDH:SPIxDL write will be ignored. SPTEF

is automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI,

data written to SPIxDH:SPIxDL is transferred to the shifter almost immediately so SPTEF is set within two bus

cycles allowing a second data to be queued into the transmit buffer. After completion of the transfer of the data

in the shift register, the queued data from the transmit buffer will automatically move to the shifter and SPTEF will

be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer,

SPTEF simply remains set and no data moves from the buffer to the shifter.

0 SPI transmit buffer not empty

1 SPI transmit buffer empty

MODF

Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low,

indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only

when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading

MODF while it is 1, then writing to SPI control register 1 (SPIxC1).

0 No mode fault error

1 Mode fault error detected

321

Bit 15

Bit 8

Reset

000

Figure 15-9. SPI Data Register High (SPIxDH)

321

Bit 7

Bit 0

Reset

000

Figure 15-10. SPI Data Register Low (SPIxDL)

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