HCS08 datasheet(249/374 Pages) NXP

249 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

249

321

SPMIE

SPIMODE

MODFEN

BIDIROE

SPISWAI

SPC0

Reset

000

= Unimplemented or Reserved

Figure 15-6. SPI Control Register 2 (SPIxC2)

Table 15-3. SPIxC2 Register Field Descriptions

Field

Description

SPMIE

SPI Match Interrupt Enable — This is the interrupt enable for the SPI receive data buffer hardware match

(SPMF) function.

0 Interrupts from SPMF inhibited (use polling).

1 When SPMF = 1, requests a hardware interrupt.

SPIMODE

SPI 8- or 16-bit Mode — This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length.

In master mode, a change of this bit will abort a transmission in progress, force the SPI system into idle state,

and reset all status bits in the SPIxS register. Refer to section Section 15.4.4, “Data Transmission Length,” for

details.

0 8-bit SPI shift register, match register, and buffers.

1 16-bit SPI shift register, match register, and buffers.

MODFEN

Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or

effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to

Table 15-2 for details)

0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI

1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output

BIDIROE

Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,

BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.

Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO

(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.

0 Output driver disabled so SPI data I/O pin acts as an input

1 SPI I/O pin enabled as an output

SPISWAI

SPI Stop in Wait Mode — This bit is used for power conservation while in wait.

0 SPI clocks continue to operate in wait mode

1 SPI clocks stop when the MCU enters wait mode

SPC0

SPI Pin Control 0 — This bit enables bidirectional pin configurations as shown in Table 15-4.

0 SPI uses separate pins for data input and data output.

1 SPI configured for single-wire bidirectional operation.

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