HCS08 datasheet(248/374 Pages) NXP

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Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

248

Freescale Semiconductor

15.3.2

SPI Control Register 2 (SPIxC2)

This read/write register is used to control optional features of the SPI system. Bits 6 and 5 are not

implemented and always read 0.

Table 15-1. SPIxC1 Field Descriptions

Field

Description

SPIE

SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)

and mode fault (MODF) events.

0 Interrupts from SPRF and MODF inhibited (use polling)

1 When SPRF or MODF is 1, request a hardware interrupt

SPE

SPI System Enable — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.

If SPE is cleared, SPI is disabled and forced into idle state, and all status bits in the SPIxS register are reset.

0 SPI system inactive

1 SPI system enabled

SPTIE

SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).

0 Interrupts from SPTEF inhibited (use polling)

1 When SPTEF is 1, hardware interrupt requested

MSTR

Master/Slave Mode Select — This bit selects master or slave mode operation.

0 SPI module configured as a slave SPI device

1 SPI module configured as a master SPI device

CPOL

Clock Polarity — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules,

the SPI modules must have identical CPOL values.

This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device.

Refer to Section 15.4.5, “SPI Clock Formats” for more details.

0 Active-high SPI clock (idles low)

1 Active-low SPI clock (idles high)

CPHA

Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral

devices. Refer to Section 15.4.5, “SPI Clock Formats” for more details.

0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer

1 First edge on SPSCK occurs at the start of the first cycle of a data transfer

SSOE

Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in

SPIxC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 15-2.

LSBFE

LSB First (Shifter Direction) — This bit does not affect the position of the MSB and LSB in the data register.

Reads and writes of the data register always have the MSB in bit 7 (or bit 15 in 16-bit mode).

0 SPI serial data transfers start with most significant bit

1 SPI serial data transfers start with least significant bit

Table 15-2. SS Pin Function

MODFEN

SSOE

Master Mode

Slave Mode

General-purpose I/O (not SPI)

Slave select input

General-purpose I/O (not SPI)

Slave select input

SS input for mode fault

Slave select input

Automatic SS output

Slave select input

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