HCS08 datasheet(244/374 Pages) NXP

244 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

244

Freescale Semiconductor

15.1.2

Features

The SPI includes these distinctive features:

•

Master mode or slave mode operation

•

Full-duplex or single-wire bidirectional mode

•

Programmable transmit bit rate

•

Double-buffered transmit and receive data register

•

Serial clock phase and polarity options

•

Slave select output

•

Mode fault error flag with CPU interrupt capability

•

Control of SPI operation during wait mode

•

Selectable MSB-first or LSB-first shifting

•

Programmable 8- or 16-bit data transmission length

•

Receive data buffer hardware match feature

15.1.3

Modes of Operation

The SPI functions in three modes, run, wait, and stop.

•

Run Mode

This is the basic mode of operation.

•

Wait Mode

SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit

located in the SPIxC2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in

Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI

clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,

but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and

transmission of a byte continues, so that the slave stays synchronized to the master.

•

Stop Mode

The SPI is inactive in stop3 mode for reduced power consumption. If the SPI is configured as a

master, any transmission in progress stops, but is resumed after the CPU goes into Run Mode. If

the SPI is configured as a slave, reception and transmission of a data continues, so that the slave

stays synchronized to the master.

The SPI is completely disabled in all other stop modes. When the CPU wakes from these stop modes, all

SPI register content will be reset.

This is a high level description only, detailed descriptions of operating modes are contained in section

Section 15.4.9, “Low Power Mode Options.”

15.1.4

Block Diagrams

This section includes block diagrams showing SPI system connections, the internal organization of the SPI

module, and the SPI clock dividers that control the master mode bit rate.

HCS08 bảng dữ liệu(PDF) 244 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 244 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL