HCS08 datasheet(247/374 Pages) NXP

247 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

247

15.2.2

MOSI — Master Data Out, Slave Data In

When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this

pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data

input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes

the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether

the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is

selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.

15.2.3

MISO — Master Data In, Slave Data Out

When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this

pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data

output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes

the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the

pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,

this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.

15.2.4

SS — Slave Select

When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as

a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being

a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select

output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select

output (SSOE = 1).

15.3

The SPI has eight 8-bit registers to select SPI options, control baud rate, report SPI status, hold an SPI data

match value, and for transmit/receive data.

Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address

assignments for all SPI registers. This section refers to registers and control bits only by their names, and

a Freescale-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

15.3.1

SPI Control Register 1 (SPIxC1)

This read/write register includes the SPI enable control, interrupt enables, and configuration options.

321

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

Reset

000

100

Figure 15-5. SPI Control Register 1 (SPIxC1)

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