HCS08 datasheet(259/374 Pages) NXP

259 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

259

SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave

select input of a slave.

Figure 15-14. SPI Clock Formats (CPHA = 0)

When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB

depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the

slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK

edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the

second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and

slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between

transfers.

15.4.6

SPI Baud Rate Generation

As shown in Figure 15-15, the clock source for the SPI baud rate generator is the bus clock. The three

prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate

select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256

to get the internal SPI master mode bit-rate clock.

The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking

place. In the other cases, the divider is disabled to decrease IDD current.

BIT TIME #

(REFERENCE)

MSB FIRST

LSB FIRST

SPSCK

(CPOL = 0)

SPSCK

(CPOL = 1)

SAMPLE IN

(MISO OR MOSI)

MOSI

(MASTER OUT)

MISO

(SLAVE OUT)

SS OUT

(MASTER)

SS IN

(SLAVE)

BIT 7

BIT 0

BIT 6

BIT 1

BIT 2

BIT 5

BIT 1

BIT 6

BIT 0

BIT 7

...

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