HCS08 datasheet(263/374 Pages) NXP

263 / 374 page

Serial Peripheral Interface (S08SPI16V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

263

NOTE

Care must be taken when expecting data from a master while the slave is in

wait or stop3 mode. Even though the shift register will continue to operate,

the rest of the SPI is shut down (i.e. a SPRF interrupt will not be generated

until exiting stop or wait mode). Also, the data from the shift register will

not be copied into the SPIxDH:SPIxDL registers until after the slave SPI has

exited wait or stop mode. A SPRF flag and SPIxDH:SPIxDL copy is only

generated if wait mode is entered or exited during a tranmission. If the slave

enters wait mode in idle mode and exits wait mode in idle mode, neither a

SPRF nor a SPIxDH:SPIxDL copy will occur.

15.4.9.3

SPI in Stop Mode

Stop3 mode is dependent on the SPI system. Upon entry to stop3 mode, the SPI module clock is disabled

(held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the

transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is

exchanged correctly. In slave mode, the SPI will stay synchronized with the master.

The stop mode is not dependent on the SPISWAI bit.

In all other stop modes, the SPI module is completely disabled. After stop, all registers are reset to their

default values, and the SPI module must be re-initialized.

15.4.9.4

Reset

The reset values of registers and signals are described in Section 15.3, “Register Definition.” which details

the registers and their bit-fields.

•

If a data transmission occurs in slave mode after reset without a write to SPIxDH:SPIxDL, it will

transmit garbage, or the data last received from the master before the reset.

•

Reading from the SPIxDH:SPIxDL after reset will always read zeros.

15.4.9.5

Interrupts

The SPI only originates interrupt requests when the SPI is enabled (SPE bit in SPIxC1 set). The following

is a description of how the SPI makes a request and how the MCU should acknowledge that request. The

interrupt vector offset and interrupt priority are chip dependent.

15.4.10 SPI Interrupts

There are four flag bits, three interrupt mask bits, and one interrupt vector associated with the SPI system.

The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode

fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI

transmit buffer empty flag (SPTEF). The SPI match interrupt enable mask bit (SPIMIE) enables interrupts

from the SPI match flag (SPMF). When one of the flag bits is set, and the associated interrupt mask bit is

set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll

the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check

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