HCS08 datasheet(349/374 Pages) NXP

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Appendix A Electrical Characteristics

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

349

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA)

Eqn. A-1

where:

TA = Ambient temperature, °C

θJA = Package thermal resistance, junction-to-ambient, °C/W

PD = Pint + PI/O

Pint = IDD × VDD, Watts — chip internal power

PI/O = Power dissipation on input and output pins — user determined

For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ

(if PI/O is neglected) is:

PD = K ÷ (TJ + 273°C)

Eqn. A-2

Solving equations 1 and 2 for K gives:

K = PD × (TA + 273°C) + θJA × (PD)2

Eqn. A-3

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring

PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by

solving equations 1 and 2 iteratively for any value of TA.

A.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early

CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.

Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels

of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body

Model (HBM) and the Charge Device Model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

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