HCS08 datasheet(293/374 Pages) NXP

293 / 374 page

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

293

Chapter 17

Universal Serial Bus Device Controller (S08USBV1)

17.1

Introduction

This chapter describes an universal serial bus device controller (S08USBV1) module that is based on the

Universal Serial Bus Specification Rev 2.0. The USB bus is designed to replace existing bus interfaces

such as RS-232, PS/2, and IEEE 1284 for PC peripherals.

The S08USBV1 module provides a single-chip solution for full-speed (12 Mbps) USB device applications,

and integrates the required transceiver with Serial Interface Engine (SIE), 3.3 V regualtor, Endpoint RAM

and other control logics.

17.1.1

Clocking Requirements

The S08USBV1 requires two clock sources, the 24 MHz bus clock and a 48 MHz reference clock. The

48 MHz clock is sourced directly from MCGOUT. To achieve the 48 MHz clock rate, the MCG must be

configured properly for PLL engaged external (PEE) mode with an external crystal.

For USB operation, examples of MCG configuration using PEE mode include:

•

2 MHz crystal – RDIV = 000 and VDIV = 0110

•

4 MHz crystal – RDIV = 001 and VDIV = 0110

17.1.2

Current Consumption in USB Suspend

In USB suspend mode, the USB device current consumption is limited to 500

μA. When the USB device

goes into suspend mode, the firmware typically enters stop3 to meet the USB suspend requirements on

current consumption.

NOTE

Enabling LVD increases current consumption in stop3. Consequently, when

trying to satisfy USB suspend requirements, disabling LVD before entering

stop3.

17.1.3

3.3 V Regulator

If using an external 3.3 V regulator as an input to VUSB33 (only when USBVREN = 0), the supply voltage,

VDD, must not fall below the input voltage at the VUSB33 pin. If using the internal 3.3 V regulator

(USBVREN = 1), do not connect an external supply to the VUSB33 pin. In this case, VDD must fall between

3.9 V and 5.5 V for the internal 3.3 V regulator to operate correctly.

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