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HCS08 bảng dữ liệu(PDF) 292 Page - NXP Semiconductors |
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HCS08 bảng dữ liệu(HTML) 292 Page - NXP Semiconductors |
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292 / 374 page ![]() Timer/PWM Module (S08TPMV3) MC9S08JM60 Series Data Sheet, Rev. 5 292 Freescale Semiconductor 16.6.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The flag is cleared by the two-step sequence described Section 16.6.2, “Description of Interrupt Operation.” |
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