HCS08 datasheet(291/374 Pages) NXP

291 / 374 page

Timer/PWM Module (S08TPMV3)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

291

to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate

whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps

to clear the interrupt flag before returning from the interrupt-service routine.

TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1)

followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence

is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new

event.

16.6.2.1

Timer Overflow Interrupt (TOF) Description

The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of

operation of the TPM system (general purpose timing functions versus center-aligned PWM operation).

The flag is cleared by the two step sequence described above.

16.6.2.1.1

Normal Case

Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not

configured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the

terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning

of counter overflow.

16.6.2.1.2

Center-Aligned PWM Case

When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to

down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF

corresponds to the end of a PWM period.

16.6.2.2

Channel Event Interrupt Description

The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,

edge-aligned PWM, or center-aligned PWM).

16.6.2.2.1

Input Capture Events

When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge

(off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the

selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described

in Section 16.6.2, “Description of Interrupt Operation.”

16.6.2.2.2

Output Compare Events

When a channel is configured as an output compare channel, the interrupt flag is set each time the main

timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step

sequence described Section 16.6.2, “Description of Interrupt Operation.”

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