HCS08 datasheet(287/374 Pages) NXP

287 / 374 page

Timer/PWM Module (S08TPMV3)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

287

16.4.2.1

Input Capture Mode

With the input-capture function, the TPM can capture the time at which an external event occurs. When

an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM

counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any

edge may be chosen as the active edge that triggers an input capture.

In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only.

When either half of the 16-bit capture register is read, the other half is latched into a buffer to support

coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually

reset by writing to the channel status/control register (TPMxCnSC).

An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request.

While in BDM, the input capture function works as configured by the user. When an external event occurs,

the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the

channel value registers and sets the flag bit.

16.4.2.2

Output Compare Mode

With the output-compare function, the TPM can generate timed pulses with programmable position,

polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an

output-compare channel, the TPM can set, clear, or toggle the channel pin.

In output compare mode, values are transferred to the corresponding timer channel registers only after both

8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so:

•

If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written

•

If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter

(end of the prescaler counting) after the second byte is written.

The coherency sequence can be manually reset by writing to the channel status/control register

(TPMxCnSC).

An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request.

16.4.2.3

Edge-Aligned PWM Mode

This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can

be used when other channels in the same TPM are configured for input capture or output compare

functions. The period of this PWM signal is determined by the value of the modulus register

(TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel

ELSnA control bit. 0% and 100% duty cycle cases are possible.

The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the

PWM signal (Figure 16-15). The time between the modulus overflow and the output compare is the pulse

width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the

PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare

forces the PWM signal high.

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