HCS08 datasheet(286/374 Pages) NXP

286 / 374 page

Timer/PWM Module (S08TPMV3)

MC9S08JM60 Series Data Sheet, Rev. 5

286

Freescale Semiconductor

When the external clock source shares the TPM channel pin, this pin should not be used for other channel

timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the

TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility

to avoid such settings.) The TPM channel could still be used in output compare mode for software timing

functions (pin controls set not to affect the TPM channel pin).

16.4.1.2

Counter Overflow and Modulo Reset

An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a

software-accessible indication that the timer counter has overflowed. The enable signal selects between

software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation

(TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one.

The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned

PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1

mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000

on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus

limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When

the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes

direction at the end of the count value set in the modulus register (that is, at the transition from the value

set in the modulus register to the next lower count value). This corresponds to the end of a PWM period

(the 0x0000 count value corresponds to the center of a period).

16.4.1.3

Counting Modes

The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the

counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As

an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with

0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.

When center-aligned PWM operation is specified, the counter counts up from 0x0000 through its terminal

count and then down to 0x0000 where it changes back to up counting. Both 0x0000 and the terminal count

value are normal length counts (one timer clock period long). In this mode, the timer overflow flag (TOF)

becomes set at the end of the terminal-count period (as the count changes to the next lower count value).

16.4.1.4

Manual Counter Reset

The main timer counter can be manually reset at any time by writing any value to either half of

TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism

in case only half of the counter was read before resetting the count.

16.4.2

Channel Mode Selection

Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers

determine the basic mode of operation for the corresponding channel. Choices include input capture,

output compare, and edge-aligned PWM.

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