HCS08 datasheet(283/374 Pages) NXP

283 / 374 page

Timer/PWM Module (S08TPMV3)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

283

16.3.5

TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)

These read/write registers contain the captured TPM counter value of the input capture function or the

output compare value for the output compare or PWM functions. The channel registers are cleared by

reset.

Table 16-6. Mode, Edge, and Level Selection

CPWMS

MSnB:MSnA

ELSnB:ELSnA

Mode

Configuration

Pin not used for TPM - revert to general

purpose I/O or other peripheral control

Input capture

Capture on rising edge

only

Capture on falling edge

only

Capture on rising or

falling edge

Output compare

Toggle output on

compare

Clear output on

compare

Set output on compare

Edge-aligned

PWM

High-true pulses (clear

output on compare)

Low-true pulses (set

output on compare)

Center-aligned

PWM

High-true pulses (clear

output on compare-up)

Low-true pulses (set

output on compare-up)

Bit 15

Bit 8

Reset

Figure 16-13. TPM Channel Value Register High (TPMxCnVH)

Bit 7

321

Bit 0

Reset

Figure 16-14. TPM Channel Value Register Low (TPMxCnVL)

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