HCS08 datasheet(289/374 Pages) NXP

289 / 374 page

Timer/PWM Module (S08TPMV3)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

289

The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle)

of the CPWM signal (Figure 16-16). If ELSnA=0, a compare occurred while counting up forces the

CPWM output signal low and a compare occurred while counting down forces the output high. The

counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down

until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.

Figure 16-16. CPWM Period and Pulse Width (ELSnA=0)

Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin

transitions are lined up at the same system clock edge. This type of PWM is also required for some types

of motor drives.

Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is

operating in up/down counting mode so this implies that all active channels within a TPM must be used in

CPWM mode when CPWMS=1.

The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure

coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers

TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers.

In center-aligned PWM mode, the TPMxCnVH:L registers are updated with the value of their write buffer

according to the value of CLKSB:CLKSA bits, so:

•

If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written

•

If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the

TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If

the TPM counter is a free-running counter, the update is made when the TPM counter changes from

0xFFFE to 0xFFFF.

When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF

interrupt (at the end of this count).

Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the

coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the

channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.

PERIOD

PULSE WIDTH

COUNT=

COUNT= 0

COUNT=

OUTPUT

COMPARE

(COUNT DOWN)

OUTPUT

COMPARE

(COUNT UP)

TPMxCHn

2 x TPMxMODH:TPMxMODL

2 x TPMxCnVH:TPMxCnVL

TPMxMODH:TPMxMODL

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