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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HCS08 bảng dữ liệu(PDF) 361 Page - NXP Semiconductors |
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HCS08 bảng dữ liệu(HTML) 361 Page - NXP Semiconductors |
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361 / 374 page  Appendix A Electrical Characteristics MC9S08JM60 Series Data Sheet, Rev. 5 Freescale Semiconductor 361 A.11 MCG Specifications Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125 °C Ambient) Num C Rating Symbol Min Typical Max Unit 1P Internal reference frequency - factory trimmed at VDD = 5 V and temperature = 25 °C fint_ft — 31.25 — kHz 2P Average internal reference frequency – untrimmed 1 1 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). fint_ut 25 32.7 41.66 kHz 3 P Average internal reference frequency Q – user trimmed fint_t 31.25 — 39.0625 kHz 4 D Internal reference startup time tirefst —60 100 μs 5— DCO output frequency range - untrimmed 1 value provided for reference: fdco_ut = 1024 X fint_ut fdco_ut 25.6 33.48 42.66 MHz 6 P DCO output frequency range - trimmed fdco_t 32 — 40 MHz 7C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Δf dco_res_t — ±0.1 ±0.2 %fdco 8C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Δf dco_res_t — ±0.2 ±0.4 %fdco 9P Total deviation of trimmed DCO output frequency over voltage and temperature Δf dco_t — +0.5 –1.0 ±2 %fdco 10 C Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 –70 °C Δf dco_t — ±0.5 ±1 %fdco 11 C FLL acquisition time 2 2 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. tfll_acquire —— 1 ms 12 D PLL acquisition time 3 3 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. tpll_acquire —— 1 ms 13 C Long term Jitter of DCO output clock (averaged over 2ms interval) 4 CJitter — 0.02 0.2 %fdco 14 D VCO operating frequency fvco 7.0 — 55.0 MHz 15 D PLL reference frequency range fpll_ref 1.0 — 2.0 MHz 16 T Long term accuracy of PLL output clock (averaged over 2 ms) fpll_jitter_2ms — 0.5905 — %fpll 17 T Jitter of PLL output clock measured over 625 ns fpll_jitter_625ns — 0.5665 — %fpll 18 D Lock entry frequency tolerance 6 Dlock ±1.49 — ±2.98 % 19 D Lock exit frequency tolerance 7 Dunl ±4.47 — ±5.97 % 20 D Lock time – FLL tfll_lock —— tfll_acquire+ 1075(1/fint_t) s 21 D Lock time – PLL tpll_lock —— tpll_acquire+ 1075(1/fpll_ref) s 22 D Loss of external clock minimum frequency – RANGE = 0 floc_low (3/5) x fint — — kHz 23 D Loss of external clock minimum frequency – RANGE = 1 floc_high (16/5) x fint — — kHz |
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