HCS08 datasheet(362/374 Pages) NXP

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Appendix A Electrical Characteristics

MC9S08JM60 Series Data Sheet, Rev. 5

362

Freescale Semiconductor

A.12 AC Characteristics

This section describes ac timing characteristics for each peripheral system.

A.12.1

Control Timing

4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

BUS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected

into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given

interval.

5 Jitter measurements are based upon a 48 MHz MCGOUT clock frequency..

6 Below D

lock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG

is already in lock, then the MCG may stay in lock.

7 Below D

unl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.

Table A-13. Control Timing

Num

Parameter

Symbol

Min

Typ1

1 Typical values are based on characterization data at V

DD = 5.0 V, 25 °C unless otherwise stated.

Max

Unit

Bus frequency (tcyc = 1/fBus)fBus

—

MHz

Internal low-power oscillator period

tLPO

700

1300

μs

External reset pulse width2

2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to

override reset requests from internal sources.

textrst

100

—

Reset low drive

trstdrv

66 x tcyc

—ns

Active background debug mode latch setup time

tMSSU

500

—

Active background debug mode latch hold time

tMSH

100

—

IRQ pulse width

Asynchronous path2

Synchronous path3

3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.

tILIH, tIHIL

100

1.5 x tcyc

——

KBIPx pulse width

Asynchronous path2

Synchronous path3

tILIH, tIHIL

100

1.5 x tcyc

——

Port rise and fall time

low output drive (PTxDS = 0), (load = 50 pF)4

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

high output drive (PTxDS = 1), (load = 50 pF)

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

4 Timing is shown with respect to 20% V

DD and 80% VDD levels. Temperature range –40 °C to 85 °C.

tRise, tFall

—

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