HCS08 datasheet(201/374 Pages) NXP

201 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

201

12.5.2.2

Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz,

Bus Frequency =16 kHz

In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz

crystal configured for an 8 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus

frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates

the sequence.

1. First, PEE must transition to PBE mode:

a) MCGC1 = 0x90 (%10010000)

– CLKS (bits 7 and 6) set to %10 in order to switch the system clock source to the external

reference clock

b) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference

clock is selected to feed MCGOUT

2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to

FBE mode:

a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1

b) BLPE/FBE: MCGC1 = 0xB8 (%10111000)

– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is

in the 31.25 kHz to 39.0625 kHz range required by the FLL. In BLPE mode, the

configuration of the RDIV does not matter because both the FLL and PLL are disabled.

Changing them only sets up the dividers for FLL usage in FBE mode

c) BLPE/FBE: MCGC3 = 0x04 (%00000100)

– PLLS (bit 6) clear to 0 to select the FLL. In BLPE mode, changing this bit only prepares the

MCG for FLL usage in FBE mode. With PLLS = 0, the VDIV value does not matter.

d) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to

FBE mode

e) FBE: Loop until PLLST (bit 5) in MCGSC is clear, indicating that the current source for the

PLLS clock is the FLL

f) FBE: Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has

acquired lock. Although the FLL is bypassed in FBE mode, it is still enabled and running.

3. Next, FBE mode transitions into FBI mode:

a) MCGC1 = 0x44 (%01000100)

– CLKS (bits7 and 6) in MCGSC1 set to %01 in order to switch the system clock to the

internal reference clock

– IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source

– RDIV (bits 5-3) set to %000, or divide-by-1 because the trimmed internal reference should

be within the 31.25 kHz to 39.0625 kHz range required by the FLL

b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been

selected as the reference clock source

c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference

clock is selected to feed MCGOUT

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