HCS08 datasheet(197/374 Pages) NXP

197 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

197

minimum power consumption, leave the internal reference disabled while in an external clock

mode.

3. After the proper configuration bits have been set, wait for the affected bits in the MCGSC register

to be changed appropriately, reflecting that the MCG has moved into the proper mode.

— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and

EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the

external clock source has finished its initialization cycles and stabilized. Typical crystal startup

times are given in Appendix A, “Electrical Characteristics”.

— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before

moving on.

— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the

CLKST bits have changed to %10 indicating the external reference clock has been

appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock

in FBE mode.

To change from FEI clock mode to FBI clock mode, follow this procedure:

1. Change the CLKS bits to %01 so that the internal reference clock is selected as the system clock

source.

2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal

reference clock has been appropriately selected.

12.5.2

MCG Mode Switching

When switching between operational modes of the MCG, certain configuration bits must be changed in

order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS,

CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or

OSCINIT) must be checked before moving on in the application software.

Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the

mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001

(divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required

frequency between 1 and 2 MHz.

The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or

PLL clock has an appropriate reference clock frequency to switch to.

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