HCS08 datasheet(198/374 Pages) NXP

198 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

198

Freescale Semiconductor

The table below shows MCGOUT frequency calculations using RDIV, BDIV, and VDIV settings for each

clock mode. The bus frequency is equal to MCGOUT divided by 2.

1R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits,

and M is the multiplier selected by the VDIV bits.

This section will include 3 mode switching examples using a 4 MHz external crystal. If using an external

clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and

PBE).

12.5.2.1

Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz,

Bus Frequency = 8 MHz

In this example, the MCG will move through the proper operational modes from FEI to PEE mode until

the 4 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in

FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset. First,

the code sequence will be described. Then a flowchart will be included which illustrates the sequence.

1. First, FEI must transition to FBE mode:

a) MCGC2 = 0x36 (%00110110)

– BDIV (bits 7 and 6) set to %00, or divide-by-1

– RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range

– HGO (bit 4) set to 1 to configure external oscillator for high gain operation

– EREFS (bit 2) set to 1, because a crystal is being used

– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active

b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit

has been initialized.

Table 12-6. MCGOUT Frequency Calculation Options

Clock Mode

fMCGOUT1

Note

FEI (FLL engaged internal)

(fint * 1024) / B

Typical fMCGOUT = 16 MHz

immediately after reset. RDIV

bits set to %000.

FEE (FLL engaged external)

(fext / R *1024) / B

fext / R must be in the range of

31.25 kHz to 39.0625 kHz

FBE (FLL bypassed external)

fext / B

fext / R must be in the range of

31.25 kHz to 39.0625 kHz

FBI (FLL bypassed internal)

fint / B

Typical fint = 32 kHz

PEE (PLL engaged external)

[(fext / R) * M] / B

fext / R must be in the range of 1

MHz to 2 MHz

PBE (PLL bypassed external)

fext / B

fext / R must be in the range of 1

MHz to 2 MHz

BLPI (Bypassed low power internal)

fint / B

BLPE (Bypassed low power external)

fext / B

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