HCS08 datasheet(205/374 Pages) NXP

205 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

205

external crystal and a maximum reference divider factor of 128, the resulting frequency of the reference

clock for the FLL is 62.5 kHz (greater than the 39.0625 kHz maximum allowed).

Care must be taken in the software to minimize the amount of time spent in this state where the FLL is

operating in this condition.

The following code sequence describes how to move from FEI mode to PEE mode until the 8 MHz crystal

reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in FEI mode out of

reset, this example also shows how to initialize the MCG for PEE mode out of reset. First, the code

sequence will be described. Then a flowchart will be included which illustrates the sequence.

1. First, FEI must transition to FBE mode:

a) MCGC2 = 0x36 (%00110110)

– BDIV (bits 7 and 6) set to %00, or divide-by-1

– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range

– HGO (bit 4) set to 1 to configure external oscillator for high gain operation

– EREFS (bit 2) set to 1, because a crystal is being used

– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active

b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit

has been initialized.

c) Block Interrupts (If applicable by setting the interrupt bit in the CCR).

d) MCGC1 = 0xB8 (%10111000)

– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock

source

– RDIV (bits 5-3) set to %111, or divide-by-128.

NOTE

8 MHz / 128 = 62.5 kHz which is greater than the 31.25 kHz to 39.0625 kHz

range required by the FLL. Therefore after the transition to FBE is

complete, software must progress through to BLPE mode immediately by

setting the LP bit in MCGC2.

– IREFS (bit 2) cleared to 0, selecting the external reference clock

e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current

source for the reference clock

f) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference

clock is selected to feed MCGOUT

2. Then, FBE mode transitions into BLPE mode:

a) MCGC2 = 0x3E (%00111110)

– LP (bit 3) in MCGC2 to 1 (BLPE mode entered)

NOTE

There must be no extra steps (including interrupts) between steps 1d and 2a.

b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR).

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