HCS08 datasheet(235/290 Pages) MOTOROLA

235 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

235

MC9S08GB/GT

14.6.3 ATD Result Data (ATDRH, ATDRL)

For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map

onto ATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB).

Figure 14-9 Left-Justified Mode

For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7–0

map onto ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB).

Figure 14-10 Right-Justified Mode

The ATD 10-bit conversion results are stored in two 8-bit result registers, ATDRH and ATDRL. The result

data is formatted either left or right justified where the format is selected using the DJM control bit in the

ATDC register. The 10-bit result data is mapped either between ATDRH bits 7–0 and ATDRL bits 7–6

(left justified), or ATDRH bits 1–0 and ATDRL bits 7–0 (right justified).

For 8-bit conversions, the 8-bit result is always located in ATDRH bits 7–0, and the ATDRL bits read 0.

For 10-bit conversions, the six unused bits always read 0.

The ATDRH and ATDRL registers are read-only.

14.6.4 ATD Pin Enable (ATDPE)

Figure 14-11 ATD Pin Enable Register (ATDPE)

ATDRH

ATDRL

ATDRH

ATDRL

Bit 7

654321

Bit 0

Read:

ATDPE7

ATDPE6

ATDPE5

ATDPE4

ATDPE3

ATDPE2

ATDPE1

ATDPE0

Write:

Reset:

00000000

RESULT

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