HCS08 datasheet(70/290 Pages) MOTOROLA

70 / 290 page

Resets, Interrupts, and System Configuration

MC9S08GB/GT

MOTOROLA

The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control

value (RTIS2:RTIS1:RTIS0) used to disable the clock source to the real-time interrupt or select one of

seven wakeup delays between 8 ms and 1.024 seconds. The 1-kHz clock source and therefore the periodic

rates have a tolerance of about

±30 percent. The RTI has a local interrupt enable, RTIE, to allow masking

of the real-time interrupt. It can be disabled by writing 0:0:0 to RTIS2:RTIS1:RTIS0 so the clock source

is disabled and no interrupts will be generated. See 5.8.6 System Real-Time Interrupt Status and

Control Register (SRTISC) for detailed information about this register.

5.8 Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space

are related to reset and interrupt systems.

Refer to the direct-page register summary in the Memory section of this data sheet for the absolute address

assignments for all registers. This section refers to registers and control bits only by their names. A

Motorola-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief

descriptions of these bits are provided here, the related functions are discussed in greater detail in

Section 3 Modes of Operation.

5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes two unimplemented bits which always read 0, four read/write bits, one

read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status,

and acknowledge IRQ events.

Figure 5-2 Interrupt Request Status and Control Register (IRQSC)

IRQEDG — Interrupt Request (IRQ) Edge Select

This read/write control bit is used to select the polarity of edges or levels on the IRQ pin that cause

IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitive to both edges

and levels or just edges. When the IRQ pin is enabled as the IRQ input and is configured to detect rising

edges, the optional pullup resistor is reconfigured as an optional pulldown resistor.

1 = IRQ is rising edge or rising edge/high-level sensitive.

0 = IRQ is falling edge or falling edge/low-level sensitive.

Bit 7

654321

Bit 0

Read:

IRQEDG

IRQPE

IRQF

IRQIE

IRQMOD

Write:

IRQACK

Reset:

00000000

= Unimplemented or Reserved

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