HCS08 datasheet(84/290 Pages) MOTOROLA

84 / 290 page

Internal Clock Generator (ICG) Module

MC9S08GB/GT

MOTOROLA

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Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or

external clock source and multiplies it to a higher frequency. Status bits provide information when

the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the

external reference clock and signals whether the clock is valid or not.

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Clock select block — The clock select block provides several switch options for connecting

different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out of

the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source, and

FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock

(XCLK). ICGLCLK is the clock source for the background debug controller (BDC).

The module is intended to be very user friendly with many of the features occurring automatically without

user intervention. To quickly configure the module, go to Initialization/Application Information and

pick an example that best suits the application needs.

6.1.1 Features

Features of the ICG and clock distribution system:

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Several options for the primary clock source allow a wide range of cost, frequency, and precision

choices:

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32 kHz–100 kHz crystal or resonator

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1 MHz–16 MHz crystal or resonator

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External clock

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Internal reference generator

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Defaults to self-clocked mode to minimize startup delays

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Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz)

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Uses external or internal clock as reference frequency

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Automatic lockout of non-running clock sources

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Reset or interrupt on loss of clock or loss of FLL lock

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Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast

frequency lock when recovering from stop3 mode

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DCO will maintain operating frequency during a loss or removal of reference clock

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Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)

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Separate self-clocked source for real-time interrupt

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Trimmable internal clock source supports SCI communications without additional external

components

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Automatic FLL engagement after lock is acquired

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