HCS08 datasheet(90/290 Pages) MOTOROLA

90 / 290 page

Internal Clock Generator (ICG) Module

MC9S08GB/GT

MOTOROLA

6.3.3 FLL Engaged, Internal Clock (FEI) Mode

FLL engaged internal (FEI) is entered when any of the following conditions occur:

•

CLKS bits are written to 01

•

The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01

In FLL engaged internal mode, the reference clock is derived from the internal reference clock

ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as

selected by the MFD bits.

6.3.3.1 FLL Engaged Internal Unlocked

FEI unlocked is a temporary state that is entered when FEI is entered and the count error (

∆n) output from

the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the

lock detector to detect the unlock condition.

The ICG will remain in this state while the count error (

∆n) is greater than the maximum n

lock or less than

the minimum nlock, as required by the lock detector to detect the lock condition.

In this state the output clock signal ICGOUT frequency is given by fICGDCLK / R.

6.3.3.2 FLL Engaged Internal Locked

FLL engaged internal locked is entered from FEI unlocked when the count error (

∆n), which comes from

the subtractor, is less than nlock (max) and greater than nlock (min) for a given number of samples, as

required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is

given by fICGDCLK / R. In FEI locked, the filter value is only updated once every four comparison cycles.

The update made is an average of the error measurements taken in the four previous comparisons.

6.3.4 FLL Bypassed, External Clock (FBE) Mode

FLL bypassed external (FBE) is entered when any of the following conditions occur:

•

From SCM when CLKS = 10 and ERCS is high

•

When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited

•

From FLL engaged external mode if a loss of DCO clock occurs and the external reference is still

valid (both LOCS = 1 and ERCS = 1)

In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,

ICGERCLK. The output clock signal ICGOUT frequency is given by fICGERCLK / R. If an external clock

source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range

0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for

RANGE = 0 or high for RANGE = 1.

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