HCS08 datasheet(36/290 Pages) MOTOROLA

36 / 290 page

Modes of Operation

MC9S08GB/GT

MOTOROLA

Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other

memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit

of stop2, these values can be restored by user software before pin latches are opened.

When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are

turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon

entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after

exiting stop2 mode until a logic 1 is written to PPDACK in SPMSC2.

Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt.

IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before

entering stop2.

Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states

remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default

reset states and must be initialized.

After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to

go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is

written to PPDACK in SPMSC2.

To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the

contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to

the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the

to their reset states.

For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that

interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before

writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O

latches are opened.

3.6.3 Stop3 Mode

Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The

ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the

internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched

at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the

pins being maintained.

Exit from stop3 is done by asserting RESET, an asynchronous interrupt pin, or through the real-time

interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.

If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after

taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in

the MCU taking the appropriate interrupt vector.

A separate self-clocked source (

≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3

mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function

HCS08 bảng dữ liệu(PDF) 36 Page - Motorola, Inc