HCS08 datasheet(64/290 Pages) MOTOROLA

64 / 290 page

Resets, Interrupts, and System Configuration

MC9S08GB/GT

MOTOROLA

5.3 MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,

most control and status registers are forced to initial values and the program counter is loaded from the

reset vector ($FFFE:$FFFF). On-chip peripheral modules are disabled and I/O pins are initially configured

as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code

pointer (SP) and system control settings. SP is forced to $00FF at reset.

The MC9S08GB/GT has seven sources for reset:

•

Power-on reset (POR)

•

Low-voltage detect (LVD)

•

Computer operating properly (COP) timer

•

Illegal opcode detect

•

Background debug forced reset

•

The reset pin (RESET)

•

Clock generator loss of lock and loss of clock reset

Each of these sources, with the exception of the background debug forced reset, has an associated bit in

the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module

switches to self-clocked mode with the frequency of fSelf_reset selected. The reset pin is driven low for 34

internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are

completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low

externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset

pin is the cause of the MCU reset.

5.4 Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute as

expected. To prevent a system reset from the COP timer (when it is enabled), application software must

reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it

times out, a system reset is generated to force the system back to a known starting point. The COP

watchdog is enabled by the COPE bit in SOPT (see 5.8.4 System Options Register (SOPT) for additional

information). The COP timer is reset by writing any value to the address of SRS. This write does not affect

the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal

to the COP timer.

After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing

as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE

bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods

(218 or 213 cycles of the bus rate clock). Even if the application will use the reset default settings in COPE

and COPT, the user should still write to write-once SOPT during reset initialization to lock in the settings.

That way, they cannot be changed accidentally if the application program gets lost.

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