HCS08 datasheet(37/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

MC9S08GB/GT

and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but

in that case the real-time interrupt cannot wake the MCU from stop.

3.6.4 Active BDM Enabled in Stop Mode

Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.

This register is described in the Development Support section of this data sheet. If ENBDM is set when

the CPU executes a STOP instruction, the system clocks to the background debug logic remain active

when the MCU enters stop mode so background debug communication is still possible. In addition, the

voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the

user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.

Most background commands are not available in stop mode. The memory-access-with-status commands

do not allow memory access, but they report an error indicating that the MCU is in either stop or wait

mode. The BACKGROUND command can be used to wake the MCU from stop and enter active

background mode if the ENBDM bit is set. Once in background debug mode, all background commands

are available. The table below summarizes the behavior of the MCU in stop when entry into the

background debug mode is enabled.

3.6.5 LVD Enabled in Stop Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops

below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in

SPMSC1 when the CPU executes a STOP instruction, then the voltage regulator remains active during

stop mode. If the user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1),

the MCU will instead enter stop3. The table below summarizes the behavior of the MCU in stop when the

LVD is enabled.

Table 3-2 BDM Enabled Stop Mode Behavior

Mode

PDC

PPDC

CPU, Digital

Peripherals,

FLASH

RAM

ICG

ATD

Regulator

I/O Pins

RTI

Stop3

Don’t

care

Don’t

care

Standby

Active

Disabled

(1)

NOTES:

1. Either ATD stop mode or power-down mode depending on the state of ATDPU.

Active

States

held

Optionally on

Table 3-3 LVD Enabled Stop Mode Behavior

Mode

PDC

PPDC

CPU, Digital

Peripherals,

FLASH

RAM

ICG

ATD

Regulator

I/O Pins

RTI

Stop3

Don’t

care

Don’t

care

Standby

Disabled

(1)

NOTES:

1. Either ATD stop mode or power-down mode depending on the state of ATDPU.

Active

States

held

Optionally on

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