| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
HCS08 bảng dữ liệu(PDF) 74 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
HCS08 bảng dữ liệu(HTML) 74 Page - Motorola, Inc |
|
74 / 290 page ![]() Resets, Interrupts, and System Configuration MC9S08GB/GT 74 MOTOROLA COPE — COP Watchdog Enable This write-once bit defaults to 1 after reset. 1 = COP watchdog timer enabled (force reset on timeout). 0 = COP watchdog timer disabled. COPT — COP Watchdog Timeout This write-once bit defaults to 1 after reset. 1 = Long timeout period selected (218 cycles of BUSCLK). 0 = Short timeout period selected (213 cycles of BUSCLK). STOPE — Stop Mode Enable This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 1 = Stop mode enabled. 0 = Stop mode disabled. BKGDPE — Background Debug Mode Pin Enable The BKGDPE bit enables the PTD0/BKGD/MS pin to function as BKGD/MS. When the bit is clear, the pin will function as PTD0, which is an output only general purpose I/O. This pin always defaults to BKGD/MS function after any reset. 1 = BKGD pin enabled. 0 = BKGD pin disabled. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |