HCS08 datasheet(92/290 Pages) MOTOROLA

92 / 290 page

Internal Clock Generator (ICG) Module

MC9S08GB/GT

MOTOROLA

If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked

status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock

condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters

the off state. Since this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up

from stop.

Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the

TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the

LOLS will not be set.

6.3.7 FLL Loss-of-Clock Detection

The reference clock and the DCO clock are monitored under different conditions (see Table 6-2). Provided

the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum

frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls

below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.

LOCS will remain set until it is acknowledged or until the MCU is reset.

If the ICG is in FEE mode when a loss of clock occurs and the ERCS is still set to 1, then the CLKST bits

are set to 10 and the ICG reverts to FBE mode.

A loss of clock will also cause a loss of lock when in FEE or FEI modes. Since the method of clearing the

LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE = 1 and

LOCRE = 0. In this case, the interrupt would be overridden by the reset for the loss of lock.

Table 6-2 Clock Monitoring

Mode

CLKS

REFST

ERCS

External

Reference Clock

Monitored?

DCO Clock

Monitored?

Off

0X or 11

Forced Low

Real-Time(1)

NOTES:

1. If ENABLE is high (waiting for external crystal start-up after exiting stop).

Yes(1)

SCM

(CLKST = 00)

Forced Low

Yes(2)

2. DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external

mode.

Forced High

Yes(2)

Real-Time

Yes

Yes(2)

Real-Time

Yes

Yes(2)

FEI

(CLKST = 01)

Forced Low

Yes

Real-Time

Yes

FBE

(CLKST = 10)

Forced High

Real-Time

Yes

FEE

(CLKST = 11)

Real-Time

Yes

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