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HCS08 bảng dữ liệu(PDF) 231 Page - Motorola, Inc |
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HCS08 bảng dữ liệu(HTML) 231 Page - Motorola, Inc |
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231 / 290 page ![]() Data Sheet — MC9S08GB60/D V1.5 MOTOROLA 231 MC9S08GB/GT 14.6.1 ATD Control (ATDC) Figure 14-5 ATD Control Register (ATDC) Writes to the ATD control register will abort the current conversion, but will not start a new conversion. ATDPU — ATD Power Up This bit provides program on/off control over the ATD, reducing power consumption when the ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress. 1 = ATD functionality. 0 = Disable the ATD and enter a low-power state. DJM — Data Justification Mode This bit determines how the 10-bit conversion result data maps onto the ATD result register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATDRH. For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map onto ATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB). Figure 14-6 Left-Justified Mode For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7–0 map onto ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB). Figure 14-7 Right-Justified Mode Bit 7 654321 Bit 0 Read: ATDPU DJM RES8 SGN PRS Write: Reset: 00000000 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 ATDRH ATDRL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 ATDRH ATDRL RESULT RESULT |
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