HCS08 datasheet(233/290 Pages) MOTOROLA

233 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

233

MC9S08GB/GT

14.6.2 ATD Status and Control (ATDSC)

Figure 14-8 ATD Status and Control Register (ATDSC)

Writes to the ATD status and control register clears the CCF flag, cancels any pending interrupts, and

initiates a new conversion.

Table 14-4 Clock Prescaler Values

PRS

Factor = (PRS +1)

× 2

Max Bus Clock

MHz

(2 MHz max ATD

Clock)(1)

NOTES:

1. Maximum ATD conversion clock frequency is 2 MHz. The max bus clock frequency is computed from the max ATD

conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD

conversion clock frequency)

× 2 (Factor) = 4 MHz.

Max Bus Clock

MHz

(1 MHz max ATD

Clock)(2)

2. Use these settings if the maximum desired ATD conversion clock frequency is 1 MHz. The max bus clock frequency is

computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max

bus clock = 1 (max ATD conversion clock frequency)

× 2 (Factor) = 2 MHz.

Min Bus Clock(3)

MHz

(500 kHz min ATD

Clock)

3. Minimum ATD conversion clock frequency is 500 kHz. The min bus clock frequency is computed from the min ATD

conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD

conversion clock frequency)

× 2 (Factor) = 1 MHz.

0000

2421

0001

4842

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Bit 7

654321

Bit 0

Read:

CCF

ATDIE

ATDCO

ATDCH

Write:

Reset:

00000001

= Unimplemented or Reserved

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