HCS08 datasheet(164/290 Pages) MOTOROLA

164 / 290 page

Timer/PWM (TPM) Module

MC9S08GB/GT

164

MOTOROLA

When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising

edges, falling edges, any edge, or no edge (off) as the edge which triggers an input capture event. When

the selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described

in 10.6.1 Clearing Timer Interrupt Flags.

When a channel is configured as an output compare channel, the interrupt flag is set each time the main

timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step

sequence described in 10.6.1 Clearing Timer Interrupt Flags.

10.6.4 PWM End-of-Duty-Cycle Events

For channels that are configured for PWM operation, there are two possibilities:

•

When the channel is configured for edge-aligned PWM, the channel flag is set when the timer

counter matches the channel value register which marks the end of the active duty cycle period.

•

When the channel is configured for center-aligned PWM, the timer count matches the channel value

at the end of the active duty cycle which are the times when the timer counter matches the channel

value register.

The flag is cleared by the 2-step sequence described in 10.6.1 Clearing Timer Interrupt Flags.

10.7 TPM Registers and Control Bits

The TPM includes:

•

An 8-bit status and control register (TPMxSC)

•

A 16-bit counter (TPMxCNTH:TPMxCNTL)

•

A 16-bit modulo register (TPMxMODH:TPMxMODL)

Each timer channel has:

•

An 8-bit status and control register (TPMxCnSC)

•

A 16-bit channel value register (TPMxCnVH:TPMxCnVL)

Refer to the direct-page register summary in the Memory section of this data sheet for the absolute address

assignments for all TPM registers. This section refers to registers and control bits only by their names. A

Motorola-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

Some MCU systems have more than one TPM, so register names include placeholder characters to identify

which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x,

channel n and TPM1C2SC is the status and control register for timer 1, channel 2.

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