HCS08 datasheet(162/290 Pages) MOTOROLA

162 / 290 page

Timer/PWM (TPM) Module

MC9S08GB/GT

162

MOTOROLA

Equation 1

pulse width = 2 x (TPMxCnVH:TPMxCnVL)

Equation 2

period = 2 x (TPMxMODH:TPMxMODL);

for TPMxMODH:TPMxMODL = $0001–$7FFF

If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will

be 0 percent. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the

(non-zero) modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never

occur. This implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF

if generation of 100 percent duty cycle is not necessary). This is not a significant limitation because the

resulting period is much longer than required for normal applications.

TPMxMODH:TPMxMODL = $0000 is a special case that should not be used with center-aligned PWM

mode. When CPWMS = 0, this case corresponds to the counter running free from $0000 through $FFFF,

but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at

$0000 in order to change directions from up-counting to down-counting.

Figure 10-4 shows the output compare value in the TPM channel registers (multiplied by 2) determines

the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up

forces the CPWM output signal low and a compare match while counting down forces the output high.

The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts

down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.

Figure 10-4 CPWM Period and Pulse Width (ELSnA = 0)

Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin

transitions are lined up at the same system clock edge. This type of PWM is also required for some types

of motor drives.

Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to

ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,

TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are

transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have

been written and the timer counter overflows (reverses direction from up-counting to down-counting at the

end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to

PWM channels, not output compares.

PERIOD

PULSE WIDTH

COUNT =

COUNT = 0

OUTPUT

COMPARE

(COUNT UP)

OUTPUT

COMPARE

(COUNT DOWN)

COUNT =

TPMxMODH:TPMxMODL

TPMxCHn

TPMxMODH:TPMxMODL

2 x TPMxCnVH:TPMxCnVL

2 x TPMxMODH:TPMxMODL

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