HCS08 datasheet(163/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

163

MC9S08GB/GT

Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a

TOF interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and

they will all update simultaneously at the start of a new period.

Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the

coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the

channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.

10.6 TPM Interrupts

The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.

The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is

configured for input capture, the interrupt flag is set each time the selected input capture edge is

recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each

time the main timer counter matches the value in the 16-bit channel value register. See the Resets,

Interrupts, and System Configuration section for absolute interrupt vector addresses, priority, and local

interrupt mask control bits.

For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer

overflow, channel input capture, or output compare events. This flag may be read (polled) by software to

determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable

hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated

whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a

sequence of steps to clear the interrupt flag before returning from the interrupt service routine.

10.6.1 Clearing Timer Interrupt Flags

TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1)

followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence

is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new

event.

10.6.2 Timer Overflow Interrupt Description

The conditions which cause TOF to become set depend on the counting mode (up or up/down). In

up-counting mode, the 16-bit timer counter counts from $0000 through $FFFF and overflows to $0000 on

the next counting clock. TOF becomes set at the transition from $FFFF to $0000. When a modulus limit

is set, TOF becomes set at the transition from the value set in the modulus register to $0000. When the

counter is operating in up/down-counting mode, the TOF flag gets set as the counter changes direction at

the transition from the value set in the modulus register and the next lower count value. This corresponds

to the end of a PWM period. (The $0000 count value corresponds to the center of a period.)

10.6.3 Channel Event Interrupt Description

The meaning of channel interrupts depends on the current mode of the channel (input capture, output

compare, edge-aligned PWM, or center-aligned PWM).

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