HCS08 datasheet(161/290 Pages) MOTOROLA

161 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

161

MC9S08GB/GT

An output compare event sets a flag bit (CHnF) which can optionally generate a CPU interrupt request.

10.5.2.3 Edge-Aligned PWM Mode

This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can

be used when other channels in the same TPM are configured for input capture or output compare

functions. The period of this PWM signal is determined by the setting in the modulus register

(TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value

ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.

As Figure 10-3 shows, the output compare value in the TPM channel registers determines the pulse width

(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the

pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare

forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output

compare forces the PWM signal high.

Figure 10-3 PWM Period and Pulse Width (ELSnA = 0)

When the channel value register is set to $0000, the duty cycle is 0 percent. By setting the timer channel

value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100 percent duty

cycle can be achieved. This implies that the modulus setting must be less than $FFFF to get 100 percent

duty cycle.

Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to

ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,

TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the

corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and

the value in the TPMxCNTH:TPMxCNTL counter is $0000. (The new duty cycle does not take effect until

the next full period.)

10.5.3 Center-Aligned PWM Mode

This type of PWM output uses the up/down-counting mode of the timer counter (CPWMS = 1). The output

compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal

and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL

should be kept in the range of $0001 to $7FFF because values outside this range can produce ambiguous

results. ELSnA will determine the polarity of the CPWM output.

PERIOD

PULSE

WIDTH

OVERFLOW

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

TPMxCHn

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