HCS08 datasheet(160/290 Pages) MOTOROLA

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Timer/PWM (TPM) Module

MC9S08GB/GT

160

MOTOROLA

operation (TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag

is equal to one.

The conditions which cause TOF to become set depend on the counting mode (up or up/down). In

up-counting mode, the main 16-bit counter counts from $0000 through $FFFF and overflows to $0000 on

the next counting clock. TOF becomes set at the transition from $FFFF to $0000. When a modulus limit

is set, TOF becomes set at the transition from the value set in the modulus register to $0000. When the

main 16-bit counter is operating in up/down-counting mode, the TOF flag gets set as the counter changes

direction at the transition from the value set in the modulus register and the next lower count value. This

corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.)

Because the HCS08 is an 8-bit architecture, a coherency mechanism is built into the timer counter for read

operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are

captured into a buffer so when the other byte is read, the value will represent the other byte of the count at

the time the first byte was read. The counter continues to count normally, but no new value can be read

from either byte until both bytes of the old count have been read.

The main timer counter can be reset manually at any time by writing any value to either byte of the timer

count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency

mechanism in case only one byte of the counter was read before resetting the count.

10.5.2 Channel Mode Selection

Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits

in the channel n status and control registers determine the basic mode of operation for the corresponding

channel. Choices include input capture, output compare, and buffered edge-aligned PWM.

10.5.2.1 Input Capture Mode

With the input capture function, the TPM can capture the time at which an external event occurs. When

an active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM

counter into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any

edge may be chosen as the active edge that triggers an input capture.

When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support

coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to

the channel status/control register (TPMxCnSC).

An input capture event sets a flag bit (CHnF) which can optionally generate a CPU interrupt request.

10.5.2.2 Output Compare Mode

With the output compare function, the TPM can generate timed pulses with programmable position,

polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an

output compare channel, the TPM can set, clear, or toggle the channel pin.

In output compare mode, values are transferred to the corresponding timer channel value registers only

after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset

by writing to the channel status/control register (TPMxCnSC).

HCS08 bảng dữ liệu(PDF) 160 Page - Motorola, Inc